Low Power 10T SRAM Design for Dynamic Power Reduction
نویسنده
چکیده
The aim of paper is to get over the problem of 6T SRAM cell where it loses its reliability at low supplies due to degraded noise margins. These is done by using a 10T SRAM where the cell uses a charge sharing technique between the transistors so that SRAM could be made more rigid against the noises that can cause damage to the cell at low power supplies and along with that charge sharing between the bit lines results in power consumption of the cell as the power required for charging bit lines are reduced which results in deduction of dynamic power budget of SRAM cell. The comparison between the power consumed by 8T and 10T SRAM is made. It shows that more power is consumed by 8T as compared to 10T SRAM. Also, the project shows the comparison between area of 8T and 10T SRAM that can be disregarded when used in millions.
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